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VGA.TXT
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1993-01-22
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3C0h: Attribute Controller: Address register
bit 0-4 Address of data register to write to port 3C0h
or read from port 3C1h (Reads only on VGA).
5 If set screen output is enabled and the palette can not be
modified, if clear screen output is disabled and the palette
can be modified.
Port 3C0h is special in that it is both address and data-write
register. Data reads happen from port 3C1h. An internal
flip-flop remembers whether it is currently acting as
address or data register.
Accesses to the attribute controller must be separated by
at least 250ns.
Reading port 3dAh will reset the flip-flop to address mode.
3C0h index 0-Fh (r/W): Attribute: Palette
bit 0 (EGA) Primary Blue
1 (EGA) Primary Green
2 (EGA) Primary Red
3 (EGA) Secondary Blue
4 (EGA) Secondary Green
5 (EGA) Secondary Red
0-5 (VGA) Index into the 256 color DAC table.
May be modified by 3C0h index 10h and 14h.
3C0h index 10h (r/W): Attribute: Mode Control Register
bit 0 Graphics mode if set, Alphanumeric mode else.
1 Monochrome mode if set, color mode else.
2 9-bit wide characters if set.
The 9th bit of characters C0h-DFh will be the same as
the 8th bit. Otherwise it will be the background color.
3 If set Attribute bit 7 is blinking, else high intensity.
5 (VGA Only) If set the PEL panning register (3C0h index 13h)
is temporarily set to 0 from when the line
compare causes a wrap around until the next
vertical retrace when the register is automatically
reloaded with the old value, else the PEL
panning register ignores line compares.
6 (VGA Only) If set pixels are 8 bits wide.
Used in 256 color modes.
7 (VGA Only) If set bit 4-5 of the index into the DAC table
are taken from port 3C0h index 14h bit 0-1,
else the bits in the palette register are used.
3C0h index 11h (r/W): Attribute: Overscan Color Register.
bit 0-5 Color of screen border. Color is defined as in the
palette registers.
Note: The EGA requires the Overscan color to be 0 in high resolution
modes.
3C0h index 12h (r/W): Attribute: Color Plane Enable Register
bit 0 Bit plane 0 is enabled if set.
1 Bit plane 1 is enabled if set.
2 Bit plane 2 is enabled if set.
3 Bit plane 3 is enabled if set.
4-5 Video Status MUX. Diagnostics use only.
Two attribute bits appear on bits 4 and 5 of the Input
Status Register 1 (3dAh).
Value EGA VGA
0 Red/Blue Bit 2/Bit 0
1 Blue'/Green Bit 5/Bit 4
2 Red'/Green' Bit 3/Bit 1
3 Bit 7/Bit 6
3C0h index 13h (r/W): Attribute: Horizontal PEL Panning Register
bit 0-3 Indicates number of pixels to shift the display left
Value 9bit textmode 256color mode Other modes
0 1 0 0
1 2 n/a 1
2 3 1 2
3 4 n/a 3
4 5 2 4
5 6 n/a 5
6 7 3 6
7 8 n/a 7
8 0 n/a n/a
3C0h index 14h (r/W): Attribute: Color Select Register (VGA Only)
bit 0-1 If 3C0h index 10h bit 7 is set these 2 bits are used
as bits 4-5 of the index into the DAC table.
2-3 These 2 bits are used as bit 6-7 of the index into the
DAC table except in 256 color mode.
Note: this register does not affect 256 color modes.
3C2h (R): Input Status #0 Register
bit 4 Status of the switch selected by the Miscellaneous Output
Register 3C2h bit 2-3. Switch high if set.
5 (EGA Only) Pin 19 of the Feature Connector (FEAT0)
is high if set
6 (EGA Only) Pin 17 of the Feature Connector (FEAT1)
is high if set
7 (EGA Only ??) If set IRQ 2 has happened due to Vertical
Retrace. Should be cleared by IRQ 2 interrupt routine
by clearing port 3d4h index 11h bit 4.
3C2h (W): Miscellaneous Output Register
bit 0 If set Color Emulation. Base Address=3Dxh
else Mono Emulation. Base Address=3Bxh.
1 Enable CPU Access to video memory if set
2-3 Clock Select
0: 14MHz(EGA) 25MHz(VGA)
1: 16MHz(EGA) 28MHz(VGA)
2: External(EGA) Reserved(VGA)
4 (EGA Only) Disable internal video drivers if set
5 When in Odd/Even modes Select High 64k bank if set
6 Horizontal Sync Polarity. Negative if set
7 Vertical Sync Polarity. Negative if set
Bit 6-7 indicates the number of lines on the display:
0=200(EGA) Reserved(VGA)
1= 400(VGA)
2=350(EGA) 350(VGA)
3= 480(VGA).
Note: Set to all zero on a hardware reset.
Note: On the VGA this register can be read from port 3CCh.
3C3h (W): Video Subsystem Enable Register
bit 0 Enables the VGA display if set
3C4h index 0 (r/W): Sequencer: Reset
bit 0 (EGA) Asynchronous Reset if clear
0 (VGA) Synchronous Reset just as bit 1
1 Synchronous Reset if clear
3C4h index 1 (r/W): Sequencer: Clocking Mode
bit 0 If set character clocks are 8 dots wide, else 9.
1 (EGA Only) If set the CRTC uses 2/5 of the clock cycles, else 4/5.
2 If set loads video serializers every other character
clock cycle, else every one.
3 If set the Dot Clock is Master Clock/2, else same as
Master Clock (See 3C2h bit 2-3). (Doubles pixels).
4 (VGA Only) If set loads video serializers every fourth
character clock cycle, else every one.
5 (VGA Only) if set turns off screen and gives all memory
cycles to the CPU interface.
3C4h index 2 (r/W): Sequencer: Map Mask Register
bit 0 Enable writes to plane 0 if set
1 Enable writes to plane 1 if set
2 Enable writes to plane 2 if set
3 Enable writes to plane 3 if set
3C4h index 3 (r/W): Sequencer: Character Map Select Register
bit 0-1 (EGA) Selects EGA Character Map (0..3) if bit 3 of
the character attribute is clear.
2-3 (EGA) Selects EGA Character Map (0..3) if bit 3 of
the character attribute is set.
0,1,4 (VGA) Selects VGA Character Map (0..7) if bit 3 of
the character attribute is clear.
2,3,5 (VGA) Selects VGA Character Map (0..7) if bit 3 of
the character attribute is set.
Character Maps are placed at:
Map no. (EGA/VGA) Map no. (VGA)
0 0k 4 8k
1 16k 5 24k
2 32k 6 40k
3 48k 7 56k
3C4h index 4 (r/W): Sequencer: Memory Mode Register
bit 0 Set if in an alphanumeric mode, clear in graphics modes.
1 Set if more than 64kbytes on the adapter.
2 Enables Odd/Even addressing mode if set.
Odd/Even mode places all odd bytes in plane 1&3, and
all even bytes in plane 0&2.
3 (VGA Only) If set address bit 0-1 selects video memory
planes (256 color mode), rather than the
Map Mask and Read Map Select Registers.
3C4h index 7 (R/W): Sequencer Horizontal Character Counter Reset Register.
(VGA Only).
Note: Undocumented by IBM. May not be available in all clones.
Note: A write to this register will cause the Horizontal Character Counter
to be held reset (=0) until a write happens to any of the Sequencer
registers index 0..6.
The Vertical Line counter is clocked by a signal derived from the
Horizontal Display Enable (which does not occur if the Horizontal
Character Counter is held reset).
Thus a write to index 7 during Vertical Retrace can stop the display
timing and allow software to